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ispLSI 3256E
(R)
In-System Programmable High Density PLD Features
* HIGH-DENSITY PROGRAMMABLE LOGIC -- 256 I/O Pins -- 12000 PLD Gates -- 512 Registers -- High Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 100 MHz Maximum Operating Frequency -- tpd = 10 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * IN-SYSTEM PROGRAMMABLE -- 5V In-System Programmable (ISPTM) using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol -- Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality -- Reprogram Soldered Devices for Faster Debugging * 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE * OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Five Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
Functional Block Diagram
ORP H3 H2
ORP
ORP G3
DQ
ORP
H1
H0
G2
G1
G0
Boundary Scan
ORP
A1 A2
OR Array
DQ
F2 F1
DQ
ORP
AND Array
DQ
A3
DQ
Twin GLB
F0
OR
DQ
ORP
DQ
B1 B2
DQ
E2 E1
ORP
Global Routing Pool B3 C0 C1 C2 C3 D0 D1 D2 D3 E0
ORP
ORP
ORP
ORP
0139A/3256E
Description
The ispLSI 3256E is a High Density Programmable Logic Device containing 512 Registers, 256 Universal I/O pins, five Dedicated Clock Input Pins, 16 Output Routing Pools (ORP) and a Global Routing Pool (GRP) which allows complete inter-connectivity between all of these elements. The ispLSI 3256E features 5V in-system programmability and in-system diagnostic capabilities. The ispLSI 3256E offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 3256E device is the Twin Generic Logic Block (Twin GLB) labelled A0, A1...H3. There are a total of 32 Twin GLBs in the ispLSI 3256E device. Each Twin GLB has 24 inputs, a programmable AND array and two OR/Exclusive-OR Arrays and eight outputs which can be configured to be either combinatorial or registered. All Twin GLB inputs come from the GRP.
Copyright (c) 2007 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
March 2007
3256e_09
1
ORP
ORP
B0
Array
E3
ORP
ORP
A0
F3
Specifications ispLSI 3256E
Functional Block Diagram
Figure 1. ispLSI 3256E Functional Block Diagram
I/O 255 I/O 253 I/O 251 I/O 249 I/O 247 I/O 245 I/O 243 I/O 241 I/O 239 I/O 237 I/O 235 I/O 233 I/O 231 I/O 229 I/O 227 I/O 225 I/O 223 I/O 221 I/O 219 I/O 217 I/O 215 I/O 213 I/O 211 I/O 209 I/O 207 I/O 205 I/O 203 I/O 201 I/O 199 I/O 197 I/O 195 I/O 193
BSCAN/ispEN
TCLK/SCLK
I/O 254 I/O 252 I/O 250 I/O 248
I/O 246 I/O 244 I/O 242 I/O 240
I/O 238 I/O 236 I/O 234 I/O 232
I/O 230 I/O 228 I/O 226 I/O 224
I/O 222 I/O 220 I/O 218 I/O 216
I/O 214 I/O 212 I/O 210 I/O 208
I/O 206 I/O 204 I/O 202 I/O 200
GOE0
GOE1
TOE
Generic Logic Blocks H3
Input Bus ORP H2 H1 ORP H0
Input Bus ORP G3 G2 ORP G1 G0
ISP and Boundary Scan TAP
I/O 198 I/O 196 I/O 194 I/O 192
TMS/MODE
TDI/SDI TRST TDO/SDO I/O 190 I/O 188 I/O 186 I/O 184 I/O 182 I/O 180 I/O 178 I/O 176 I/O 174 I/O 172 I/O 170 I/O 168 I/O 166 I/O 164 I/O 162 I/O 160 I/O 191 I/O 189 I/O 187 I/O 185 I/O 183 I/O 181 I/O 179 I/O 177 I/O 175 I/O 173 I/O 171 I/O 169 I/O 167 I/O 165 I/O 163 I/O 161
Input Bus
A1
F2
I/O 25 I/O 27 I/O 29 I/O 31
I/O 24 I/O 26 I/O 28 I/O 30
ORP
A3
F0
Input Bus
B1
E2
I/O 57 I/O 59 I/O 61 I/O 63
I/O 56 I/O 58 I/O 60 I/O 62
ORP
ORP
I/O 49 I/O 51 I/O 53 I/O 55
I/O 48 I/O 50 I/O 52 I/O 54
Input Bus
I/O 41 I/O 43 I/O 45 I/O 47
I/O 40 I/O 42 I/O 44 I/O 46
ORP
ORP
I/O 33 I/O 35 I/O 37 I/O 39
I/O 32 I/O 34 I/O 36 I/O 38
Global Routing Pool (GRP)
B0 E3
ORP
I/O 17 I/O 19 I/O 21 I/O 23
I/O 16 I/O 18 I/O 20 I/O 22
A2
F1
Input Bus
I/O 9 I/O 11 I/O 13 I/O 15
I/O 8 I/O 10 I/O 12 I/O 14
ORP
ORP
I/O 1 I/O 3 I/O 5 I/O 7
I/O 0 I/O 2 I/O 4 I/O 6
A0
F3
I/O 158 I/O 156 I/O 154 I/O 152 I/O 150 I/O 148 I/O 146 I/O 144 I/O 142 I/O 140 I/O 138 I/O 136 I/O 134 I/O 132 I/O 130 I/O 128
I/O 159 I/O 157 I/O 155 I/O 153 I/O 151 I/O 149 I/O 147 I/O 145 I/O 143 I/O 141 I/O 139 I/O 137 I/O 135 I/O 133 I/O 131 I/O 129
B2
E1
B3
E0
C0
Megablock
C1 ORP
C2
C3 ORP
D0
D1 ORP
D2
D3 ORP
CLK 0 CLK 1 CLK 2 IOCLK 1 IOCLK 0
Input Bus
RESET
I/O 97 I/O 96 I/O 99 I/O 98 I/O 101 I/O 100 I/O 103 I/O 102
Input Bus
I/O 104 I/O 106 I/O 108 I/O 110
I/O 112 I/O 114 I/O 116 I/O 118
I/O 120 I/O 122 I/O 124 I/O 126
I/O 64 I/O 66 I/O 68 I/O 70
I/O 72 I/O 74 I/O 76 I/O 78
I/O 80 I/O 82 I/O 84 I/O 86
I/O 88 I/O 90 I/O 92 I/O 94
Y0 Y1 Y2 Y3 Y4
0139isp/3256E
I/O 65 I/O 67 I/O 69 I/O 71
I/O 73 I/O 75 I/O 77 I/O 79
I/O 81 I/O 83 I/O 85 I/O 87
I/O 89 I/O 91 I/O 93 I/O 95
I/O 105 I/O 107 I/O 109 I/O 111
I/O 113 I/O 115 I/O 117 I/O 119
2
I/O 121 I/O 123 I/O 125 I/O 127
Specifications ispLSI 3256E
Description (continued)
All local logic block outputs are brought back into the GRP so they can be connected to the inputs of any other logic block on the device. The device also has 256 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, a registered input, a latched input, an output or a bidirectional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. The 256 I/O Cells are grouped into 16 sets of 16 bits. Pairs of these I/O groups are associated with a logic Megablock through the use of the ORP. Each Megablock is able to provide one Product Term Output Enable (PTOE) signal which is globally distributed to all I/O cells. That PTOE signal can be generated within any GLB in the Megablock. Each I/O cell can select either a Global OE or a PTOE. Four Twin GLBs, 32 I/O Cells and two ORPs are connected together to make a logic Megablock. The Megablock is defined by the resources that it shares. The outputs of the four Twin GLBs are connected to a set of 32 I/O cells by the ORP. The ispLSI 3256E device contains eight of these Megablocks. The GRP has as its inputs the outputs from all of the Twin GLBs and all of the inputs from the bidirectional I/O cells. All of these signals are made available to the inputs of the Twin GLBs. Delays through the GRP have been equalized to minimize timing skew and logic glitching. Clocks in the ispLSI 3256E device are provided through five dedicated clock pins. The five pins provide three clocks to the Twin GLBs and two clocks to the I/O cells. The table below lists key attributes of the device along with the number of resources available. An additional feature of the ispLSI 3256E is its Boundary Scan capability, which is composed of cells connected between the on-chip system logic and the device's input and output pins. All I/O pins have associated boundary scan registers, with 3-state I/O using three boundary scan registers and inputs using one. The ispLSI 3256E supports all IEEE 1149.1 mandatory instructions, which include BYPASS, EXTEST and SAMPLE.
Key Attributes of the ispLSI 3256E
Attribute Twin GLBs Registers I/O Pins Global Clocks Global OE Test OE Quantity 32 512 256 5 2 1
Table - 003/3256E
3
Specifications ispLSI 3256E
Absolute Maximum Ratings 1
Supply Voltage Vcc ........................................................................... -0.5 to +7.0V Input Voltage Applied ........................................................................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..................................................... -2.5 to VCC +1.0V Storage Temperature ........................................................................ -65 to 150C Case Temp. with Power Applied ...................................................... -55 to 125C Max. Junction Temp. (TJ) with Power Applied (304-Pin PQFP) ...... 150C Max. Junction Temp. (TJ) with Power Applied (320-Ball BGA) ........ 140C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
SYMBOL PARAMETER Ambient Temperature Supply Voltage Input Low Voltage Input High Voltage MIN. 0 4.75 0 2.0 MAX. 70 5.25 0.8 VCC +1 UNITS C V V V
Table 2-0005/3256E
TA VCC VIL VIH
Capacitance (TA=25C,f=1.0 MHz)
SYMBOL PARAMETER I/O Capacitance Clock Capacitance TYPICAL 10 15 UNITS pf pf TEST CONDITIONS VCC = 5.0V, VI/O = 2.0V VCC = 5.0V, VY = 2.0V
Table 2-0006/3256E
C1 C2
Data Retention Specifications
PARAMETER Data Retention ispLSI Erase/Reprogram Cycles MINIMUM 20 10000 MAXIMUM - - UNITS Years Cycles
Table 2-0008/3256E
4
Specifications ispLSI 3256E
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See Figure 2
Table 2-0003/3256E
Figure 2. Test Load
+ 5V R1 Device Output R2 CL* Test Point
Output Load conditions (See Figure 2)
*CL includes Test Fixture and Probe Capacitance.
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
Table 2 - 0004A
0213A
C
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Bscan/ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current CONDITION IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) 3.5V VIN VCC 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fTOGGLE = 1 MHz MIN. - 2.4 - - - - - - TYP. - - - - - - - 300
3
MAX. UNITS 0.4 - -10 10 -150 -150 -200 - V V A A A A mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2,4
Table 2 - 0007isp/3256E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using sixteen 16-bit counters. 3. Typical values are at VCC = 5V and TA = 25C. 4. Maximum ICC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this datasheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC.
5
Specifications ispLSI 3256E
External Switching Characteristics1, 2, 3
Over Recommended Operating Conditions
PARAMETER TEST5 COND.
#2
DESCRIPTION1
-100 -- -- 100 77.0 100 5.5 -- 0.0 6.5 -- 0.0 -- 6.5 -- -- -- -- -- -- 5.0 5.0 4.5 0.0 10.0 13.0 -- -- -- -- 6.5 -- -- 7.0 -- 13.5 -- 16.0 16.0 9.0 9.0 12.0 12.0 -- -- -- -- -- --
-70 15.0 18.0 -- -- -- -- 9.0 -- -- 10.0 -- 15.0 -- 19.0 19.0 12.0 12.0 15.0 15.0 -- -- -- --
MIN. MAX. MIN. MAX.
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis ttoeen ttoedis twh twl tsu3 th3
1. 2. 3. 4. 5.
A A A -- -- -- A -- -- -- -- A -- B C B C -- -- -- -- -- --
1 Data Prop. Delay, 4PT Bypass, ORP Bypass 2 Data Propagation Delay 3 Clock Frequency with Internal Feedback3 4 Clock Freq. with Ext. Feedback,1/(tsu2 + tco1) 5 Clock Frequency, Max Toggle
4
70.0 50.0 83.0 9.0 -- 0.0 11.0 -- 0.0 -- 12.0 -- -- -- -- -- -- 6.0 6.0 5.0 0.0
6 GLB Reg. Setup Time before Clock, 4PT bypass 7 GLB Reg. Clock to Output Delay, ORP bypass 8 GLB Reg. Hold Time after Clock, 4PT bypass 9 GLB Reg. Setup Time before Clock 10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 Test OE Output Enable 19 Test OE Output Disable 20 Ext. Sync. Clock Pulse Duration, High 21 Ext. Sync. Clock Pulse Duration, Low 22 I/O Reg. Setup Time before Ext. Sync. Clock (Y3, Y4) 23 I/O Reg. Hold Time after Ext. Sync. Clock (Y3, Y4)
Unless noted otherwise, all parameters use 20 PTXOR path and ORP. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. fmax (Toggle) may be less than 1/(twh + twl). This is to allow for a clock duty cycle of other than 50%. Reference Switching Test Conditions section.
Timing Ext.3256E.eps
6
Specifications ispLSI 3256E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
#2
DESCRIPTION
-100 MIN. -- -- 4.8 -1.6 -- -- -- -- -- -- -- -- -- 0.3 5.0 -- -- -- -- 3.0 -- -- MAX. 2.4 10.3 -- -- 5.8 5.8 2.3 3.2 3.1 4.0 4.1 4.3 1.5 -- -- 1.6 5.2 4.0 6.5 3.6 1.2 0.7
-70 MIN. -- -- 5.8 -2.5 -- -- -- -- -- -- -- -- -- 1.2 7.6 -- -- -- -- 3.4 -- -- MAX. 4.0 14.0 -- -- 8.5 7.5 3.2 3.6 4.8 5.1 5.2 5.7 1.6 -- -- 3.0 5.2 4.4 6.9 4.2 1.9 0.9
UNITS
Inputs
tiobp tiolat tiosu tioh tioco tior
GRP
24 I/O Register Bypass 25 I/O Latch Delay 26 I/O Register Setup Time before Clock 27 I/O Register Hold Time after Clock 28 I/O Register Clock to Out Delay 29 I/O Register Reset to Out Delay 30 GRP Delay 31 4 Product Term Bypass Path Delay (Comb.) 32 4 Product Term Bypass Path Delay (Reg.) 33 1 Product Term/XOR Path Delay 34 20 Product Term/XOR Path Delay 35 XOR Adjacent Path Delay3 36 GLB Register Bypass Delay 37 GLB Register Setup Time before Clock 38 GLB Register Hold Time after Clock 39 GLB Register Clock to Output Delay 40 GLB Register Reset to Output Delay 41 GLB Product Term Reset to Register Delay 42 GLB Product Term Output Enable to I/O Cell Delay 43 GLB Product Term Clock Delay 44 ORP Delay 45 ORP Bypass Delay
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp
GLB
t4ptbp t4ptbr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck ORP torp torpbp
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Timing Int.3256E.eps
7
Specifications ispLSI 3256E
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER
#2
DESCRIPTION
-100 MIN. -- -- -- -- 1.6 0.3 -- -- -- MAX. 2.6 17.6 5.5 5.5 1.6 1.6 4.5 5.9 6.1
-70 MIN. -- -- -- -- 1.8 0.8 -- -- -- MAX. 3.3 18.3 5.7 5.7 1.8 2.5 4.6 7.5 8.9
UNITS
Outputs
tob tobs toen todis
Clocks
46 Output Buffer Delay 47 Output Buffer Delay, Slew Limited Adder 48 I/O Cell OE to Output Enabled 49 I/O Cell OE to Output Disabled 50 Clock Delay, Y0 or Y1 or Y2 to Global GLB Clk Line 51 Clock Delay, Y3 or Y4 to I/O Cell Global Clock Line 52 Global Reset to GLB and I/O Registers 53 Global OE Pad Buffer 54 Test OE Pad Buffer
ns ns ns ns ns ns ns ns ns
tgy0/1/2 tioy3/4
Global Reset
tgr tgoe ttoe
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Timing Int.2.3256E.eps
8
Specifications ispLSI 3256E
ispLSI 3256E Timing Model
I/O Cell GRP Feedback #31 GLB ORP I/O Cell
I/O Pin (Input)
I/O Reg Bypass #24 Input D Register Q RST #25 - 29
GRP #30
4 PT Bypass #32 20 PT XOR Delays #33 - 35 #52
GLB Reg Bypass #36 GLB Reg Delay D RST Q #37 - 40
ORP Bypass #45 ORP Delay #44
#46, 47
I/O Pin (Output)
#52 Reset Y3,4
#48, 49
#51 Control RE PTs OE #41 - 43 CK
Y0,1,2
#50
GOE0,1 TOE
#53 #54
0902/3256E
Derivations of tsu, th and tco from the Product Term Clock 1 tsu
= = = 1.4 ns = = = = 4.5 ns = = = = 13.7 ns = Logic + Reg su - Clock (min) (tiobp + tgrp + t20ptxor) + (tgsu) - (tiobp + tgrp + tptck(min)) (#24+ #30+ #34) + (#37) - (#24+ #30+ #43) (2.4 + 2.3 + 4.1) + (0.3) - (2.4 + 2.3 + 3.0) Clock (max) + Reg h - Logic (tiobp + tgrp + tptck(max)) + (tgh) - (tiobp + tgrp + t20ptxor) (#24+ #30+ #43) + (#38) - (#24+ #30+ #34) (2.4 + 2.3 + 3.6) + (5.0) - (2.4 + 2.3 + 4.1) Clock (max) + Reg co + Output (tiobp + tgrp + tptck(max)) + (tgco) + (torp + tob) (#24 + #30 + #43) + (#39) + (#44 + #46) (2.4 + 2.3 + 3.6) + (1.6) + (1.2 + 2.6)
Table 2- 0042-3256E
th
tco
Note: Calculations are based upon timing specifications for the ispLSI 3256E-100L.
9
Specifications ispLSI 3256E
Power Consumption
Power consumption in the ispLSI 3256E device depends on two primary factors: the speed at which the device is operating and the number of product terms used. Figure 3. Typical Device Power Consumption vs fmax
600 500
ispLSI 3256E
Figure 3 shows the relationship between power and operating speed.
ICC (mA)
400 300 200 0
20
40
60
80
100
fmax (MHz)
Notes: Configuration of 16 16-bit Counters Typical Current at 5V, 25 C
ICC can be estimated for the ispLSI 3256E using the following equation: ICC = 60 + (# of PTs * 0.48) + (# of nets * Max. freq * 0.0106) where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max. freq = Highest Clock Frequency to the device The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127/3256E
10
Specifications ispLSI 3256E
Pin Description
Pin Name I/O GOE0, GOE1 TOE RESET Y0, Y1, Y2 Y3, Y4 BSCAN/ispEN Description Input/Output pins - These are the general purpose I/O pins used by the logic array. Global Output Enable input pins. Test Output Enable pin - This pin tristates all I/O pins when a logic low is driven. Active Low (0) Reset pin - Resets all of the GLB and I/O registers in the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the GLBs on the device. Dedicated Clock inputs. These clock inputs are connected to one of the clock inputs of all the I/O cells on the device. Input - Dedicated in-system programming enable input pin. When this pin is high, the BSCAN TAP controller pins TMS, TDI, TDO and TCK are enabled. When this pin is brought low, the ISP State Machine control pins MODE, SDI, SDO and SCLK are enabled. High-to-low transition of this pin will put the device in the programming mode and put all I/O pins in the high-Z state. Input - This pin performs two functions. It is the Test Data input pin when ispEN is logic high. When ispEN is logic low, it functions as an input pin to load programming data into the device. SDI is also used as one of the two control pins for the ISP State Machine. Input - This pin performs two functions. It is the Test Clock input pin when ispEN is logic high. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. Input - This pin performs two functions. It is the Test Mode Select input pin when ispEN is logic high. When ispEN is logic low, it functions as a pin to control the operation of the ISP State Machine. Input - Test Reset, active low to reset the Boundary Scan State Machine. Output - This pin performs two functions. When ispEN is logic low, it functions as the pin to read the ISP data. When ispEN is high, it functions as Test Data Out. Ground (GND) Vcc No Connect.
TDI/SDI
TCK/SCLK TMS/MODE TRST/NC1 TDO/SDO GND VCC NC1
1. NC pins are not to be connected to any active signals, VCC or GND.
Pin Locations
Signal GOE0, GOE1 TOE RESET ispEN/BSCAN SDI/TDI SCLK/TCK MODE/TMS TRST/NC1 SDO/TDO GND VCC NC1
1. NC pins are not to be connected to any active signals, VCC or GND.
304-Pin PQFP 195, 185 215 53 63 23 73 13 225 155 9, 19, 39, 49, 69, 85, 95, 115, 125, 145, 161, 171, 191, 201, 221, 237, 247, 267, 277, 297 1, 29, 59, 77, 105, 135, 153, 181, 211, 229, 257, 287, 304 AD11, AC14 AC6 A17
320-Ball BGA
Y0, Y1, Y2, Y3, Y4 43, 33, 205, 175, 165
A14, B11, AD8, AB16, AA18 B19 C9 D20 D7 AA5 AB21 D6, C8, B13, A16, D19, F21, H22, N23, T24, W21, AA19, AB17, AC12, AD9, AA6, W4, U3, M2, J1, F4 D4, B10, B18, D21, K23, V23, AA21, AC15, AC7, AA4, R2, G2, C3 A1, A2, A23, A24, B1, B2, B23, B24, AC1, AC2, AC23, AC24, AD1, AD2, AD23, AD24
11
Specifications ispLSI 3256E
I/O Locations
Signal PQFP BGA Signal PQFP BGA Signal PQFP BGA Signal PQFP BGA Signal PQFP BGA
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52
40 41 42 44 45 46 47 48 50 51 52 54 55 56 57 58 60 61 62 64 65 66 67 68 70 71 72 74 75 76 78 79 80 81 82 83 84 86 87 88 89 90 91 92 93 94 96 97 98 99 100 101 102
C13 D13 A13 B14 C14 D14 A15 B15 C15 D15 B16 C16 B17 D16 A18 C17 A19 D17 C18 A20 D18 C19 B20 A21 C20 B21 A22 C21 B22 C22 C23 D22 C24 E21 D23 E22 D24 E23 F22 E24 G21 F23 G22 F24 H21 G23 G24 J21 H23 J22 H24 J23 K21
I/O 53 I/O 54 I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97 I/O 98 I/O 99 I/O 100 I/O 101 I/O 102 I/O 103 I/O 104 I/O 105
103 104 106 107 108 109 110 111 112 113 114 116 117 118 119 120 121 122 123 124 126 127 128 129 130 131 132 133 134 136 137 138 139 140 141 142 143 144 146 147 148 149 150 151 152 154 156 157 158 159 160 162 163
K22 J24 K24 L21 L22 L23 L24 M24 M21 M22 M23 N22 N21 N24 P24 P23 P22 P21 R24 R23 R22 R21 T23 U24 T22 U23 T21 V24 U22 W24 U21 V22 W23 Y24 V21 W22 Y23 AA24 Y22 AA23 AB24 Y21 AA22 AB23 AB22 AC22 AD22 AA20 AC21 AB20 AD21 AC20 AB19
I/O 106 I/O 107 I/O 108 I/O 109 I/O 110 I/O 111 I/O 112 I/O 113 I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 I/O 128 I/O 129 I/O 130 I/O 131 I/O 132 I/O 133 I/O 134 I/O 135 I/O 136 I/O 137 I/O 138 I/O 139 I/O 140 I/O 141 I/O 142 I/O 143 I/O 144 I/O 145 I/O 146 I/O 147 I/O 148 I/O 149 I/O 150 I/O 151 I/O 152 I/O 153 I/O 154 I/O 155 I/O 156 I/O 157 I/O 158
164 166 167 168 169 170 172 173 174 176 177 178 179 180 182 183 184 186 187 188 189 190 192 193 194 196 197 198 199 200 202 203 204 206 207 208 209 210 212 213 214 216 217 218 219 220 222 223 224 226 227 228 230
AD20 AC19 AB18 AD19 AA17 AC18 AD18 AA16 AC17 AD17 AC16 AA15 AB15 AD16 AD15 AA14 AB14 AD14 AD13 AA13 AB13 AC13 AB12 AA12 AD12 AC11 AB11 AA11 AD10 AC10 AB10 AA10 AC9 AB9 AC8 AA9 AD7 AB8 AD6 AA8 AB7 AD5 AA7 AB6 AC5 AD4 AB5 AC4 AD3 AB4 AC3 AB3 AB2
I/O 159 I/O 160 I/O 161 I/O 162 I/O 163 I/O 164 I/O 165 I/O 166 I/O 167 I/O 168 I/O 169 I/O 170 I/O 171 I/O 172 I/O 173 I/O 174 I/O 175 I/O 176 I/O 177 I/O 178 I/O 179 I/O 180 I/O 181 I/O 182 I/O 183 I/O 184 I/O 185 I/O 186 I/O 187 I/O 188 I/O 189 I/O 190 I/O 191 I/O 192 I/O 193 I/O 194 I/O 195 I/O 196 I/O 197 I/O 198 I/O 199 I/O 200 I/O 201 I/O 202 I/O 203 I/O 204 I/O 205 I/O 206 I/O 207 I/O 208 I/O 209 I/O 210 I/O 211
231 232 233 234 235 236 238 239 240 241 242 243 244 245 246 248 249 250 251 252 253 254 255 256 258 259 260 261 262 263 264 265 266 268 269 270 271 272 273 274 275 276 278 279 280 281 282 283 284 285 286 288 289
AA3 AB1 Y4 AA2 Y3 AA1 Y2 W3 Y1 V4 W2 V3 W1 U4 V2 V1 T4 U2 T3 U1 T2 R4 R3 T1 R1 P4 P3 P2 P1 N1 N4 N3 N2 M3 M4 M1 L1 L2 L3 L4 K1 K2 K3 K4 J2 H1 J3 H2 J4 G1 H3 F1 H4
I/O 212 I/O 213 I/O 214 I/O 215 I/O 216 I/O 217 I/O 218 I/O 219 I/O 220 I/O 221 I/O 222 I/O 223 I/O 224 I/O 225 I/O 226 I/O 227 I/O 228 I/O 229 I/O 230 I/O 231 I/O 232 I/O 233 I/O 234 I/O 235 I/O 236 I/O 237 I/O 238 I/O 239 I/O 240 I/O 241 I/O 242 I/O 243 I/O 244 I/O 245 I/O 246 I/O 247 I/O 248 I/O 249 I/O 250 I/O 251 I/O 252 I/O 253 I/O 254 I/O 255
290 291 292 293 294 295 296 298 299 300 301 302 303 2 3 4 5 6 7 8 10 11 12 14 15 16 17 18 20 21 22 24 25 26 27 28 30 31 32 34 35 36 37 38
G3 F2 E1 G4 F3 E2 D1 E3 D2 C1 E4 D3 C2 B3 C4 A3 D5 B4 C5 A4 B5 C6 A5 B6 C7 A6 D8 B7 A7 D9 B8 A8 B9 D10 C10 A9 A10 D11 C11 A11 A12 D12 C12 B12
12
Specifications ispLSI 3256E
Pin Configuration
ispLSI 3256E 304-Pin PQFP Pinout Diagram
VCC I/O 224 I/O 223 I/O 222 I/O 221 I/O 220 I/O 219 GND I/O 218 I/O 217 I/O 216 I/O 215 I/O 214 I/O 213 I/O 212 I/O 211 I/O 210 VCC I/O 209 I/O 208 I/O 207 I/O 206 I/O 205 I/O 204 I/O 203 I/O 202 I/O 201 GND I/O 200 I/O 199 I/O 198 I/O 197 I/O 196 I/O 195 I/O 194 I/O 193 I/O 192 GND I/O 191 I/O 190 I/O 189 I/O 188 I/O 187 I/O 186 I/O 185 I/O 184 I/O 183 VCC I/O 182 I/O 181 I/O 180 I/O 179 I/O 178 I/O 177 I/O 176 I/O 175 I/O 174 GND I/O 173 I/O 172 I/O 171 I/O 170 I/O 169 I/O 168 I/O 167 I/O 166 I/O 165 GND I/O 164 I/O 163 I/O 162 I/O 161 I/O 160 I/O 159 I/O 158 VCC 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229
VCC I/O 225 I/O 226 I/O 227 I/O 228 I/O 229 I/O 230 I/O 231 GND I/O 232 I/O 233 I/O 234 MODE/TMS I/O 235 I/O 236 I/O 237 I/O 238 I/O 239 GND I/O 240 I/O 241 I/O 242 SDI/TDI I/O 243 I/O 244 I/O 245 I/O 246 I/O 247 VCC I/O 248 I/O 249 I/O 250 Y1 I/O 251 I/O 252 I/O 253 I/O 254 I/O 255 GND I/O 0 I/O 1 I/O 2 Y0 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 GND I/O 8 I/O 9 I/O 10 RESET I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 VCC I/O 16 I/O 17 I/O 18 ispEN/BSCAN I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 GND I/O 24 I/O 25 I/O 26 SCLK/TCK I/O 27 I/O 28 I/O 29
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
ispLSI 3256E
Top View
228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153
I/O 157 I/O 156 I/O 155 TRST/NC1 I/O 154 I/O 153 I/O 152 GND I/O 151 I/O 150 I/O 149 I/O 148 I/O 147 TOE I/O 146 I/O 145 I/O 144 VCC I/O 143 I/O 142 I/O 141 I/O 140 I/O 139 Y2 I/O 138 I/O 137 I/O 136 GND I/O 135 I/O 134 I/O 133 I/O 132 I/O 131 GOE0 I/O 130 I/O 129 I/O 128 GND I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 GOE1 I/O 122 I/O 121 I/O 120 VCC I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 Y3 I/O 114 I/O 113 I/O 112 GND I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 Y4 I/O 106 I/O 105 I/O 104 GND I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 SDO/TDO I/O 98 VCC
1. NC pins are not to be connected to any active signals, VCC or GND.
VCC I/O 30 I/O 31 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 GND I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 GND I/O 46 I/O 47 I/O 48 I/O 49 I/O 50 I/O 51 I/O 52 I/O 53 I/O 54 VCC I/O 55 I/O 56 I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 GND I/O 64 I/O 65 I/O 66 I/O 67 I/O 68 I/O 69 I/O 70 I/O 71 I/O 72 GND I/O 73 I/O 74 I/O 75 I/O 76 I/O 77 I/O 78 I/O 79 I/O 80 I/O 81 VCC I/O 82 I/O 83 I/O 84 I/O 85 I/O 86 I/O 87 I/O 88 I/O 89 I/O 90 GND I/O 91 I/O 92 I/O 93 I/O 94 I/O 95 I/O 96 I/O 97
77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152
13
Specifications ispLSI 3256E
Signal Configuration
ispLSI 3256E 320-Ball BGA Signal Diagram
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD
NC1 NC1 I/O 32 I/O 36 I/O 39 I/O 43 I/O 46 I/O 50 I/O 54 I/O 55 I/O 59 I/O 60 I/O 66 I/O 67 I/O 71 GND I/O 76 I/O 80 I/O 82 I/O 86 I/O 90 I/O 93 NC1 NC1 NC1 NC1 I/O 30 I/O 34 I/O 37 I/O 41 I/O 45 I/O 48 I/O 51 VCC I/O 58 I/O 63 GND I/O 68 I/O 72 I/O 75 I/O 78 VCC I/O 85 I/O 89 I/O 92 I/O 96 NC1 NC1 I/O 26 I/O 28 I/O 29 I/O 31 I/O 35 I/O 38 I/O 42 GND I/O 49 I/O 53 I/O 57 I/O 62 I/O 64 I/O 69 I/O 73 I/O 77 I/O 81 I/O 84 I/O 88 I/O 91 I/O 95 I/O 23 I/O 25 I/O 27 VCC I/O 33 GND I/O 40 I/O 44 I/O 47 I/O 52 I/O 56 I/O 61 I/O 65 I/O 70 I/O 74 I/O 79 I/O 83 I/O 87 GND I/O 94 I/O VCC 100 GND I/O 105 I/O 107 I/O 109 Y4 I/O 110 I/O 113 Y3 I/O 117 I/O 118 I/O 121 I/O 122 I/O 125 I/O 126 I/O 129 I/O 128 I/O 133 I/O 132 I/O 137 I/O 136 I/O 135 I/O 141 I/O 139 I/O 138 I/O 145 I/O 143 I/O GND 148 I/O 146 I/O 149
TRST/ NC1
9
I/O 247 I/O 244
8
I/O 243 I/O 242
7
I/O 240 I/O 239
6
I/O 237 I/O 235 I/O 233
5
I/O 234 I/O 232 I/O 230
4
I/O 231 I/O 229
3
I/O 227 I/O 225
2
NC1 NC1 I/O 224 I/O 220 I/O 217 I/O 213
1
NC1 NC1 I/O 221 I/O 218 I/O 214 I/O 210
I/O 19 I/O 22 I/O 24
SCLK/ TCK
I/O 16
ispEN/ BSCAN
I/O 14 VCC I/O 18 I/O 20
RESET
GND I/O 10 I/O 11 I/O 13
I/O 6 I/O 7 I/O 8 I/O 9
Y0 I/O 3 I/O 4 I/O 5
I/O 2 GND I/O 0 I/O 1
I/O 252 I/O 255 I/O 254 I/O 253
I/O 251 Y1 I/O 250 I/O 249
I/O 248 VCC I/O 246 I/O 245
A B C D E F G H J K L M N P R T U V W Y AA AB AC AD
I/O 12 I/O 15 I/O 17
I/O 21 GND
SDI/ I/O GND TDI 236 I/O 241 I/O 238
MODE/ TMS
I/O VCC 226
I/O I/O GND 228 VCC 223 I/O 222 GND I/O 215 I/O 211 I/O 207 I/O 202 I/O 198 I/O 219 I/O 216 I/O 212 I/O 209 I/O 205 I/O 201 I/O 197
I/O VCC 208 I/O 206 I/O 204
I/O 203 GND I/O 200 I/O 196 I/O 199 I/O 195
ispLSI 3256E
Bottom View
I/O 193 I/O 189 I/O 184 I/O 180 I/O 175
I/O I/O 192 GND 194 I/O 190 I/O 185 I/O 181 I/O 177 I/O 191 I/O 186 VCC I/O 179 I/O 188 I/O 187 I/O 183 I/O 182 I/O 178 I/O 174 I/O 171 I/O 167 I/O 164 I/O 160 NC1 NC1
I/O I/O 172 GND 176 I/O 168 I/O 170 I/O 173 I/O 169 I/O 165 I/O 162 I/O 158 NC1 NC1
I/O GND 166 I/O 161 I/O 163
I/O VCC 159 I/O 155 I/O 153 I/O 151 I/O 157 I/O 156 I/O 154
I/O SDO/ I/O 97 TDO 102 I/O 98 I/O 99 I/O 101 I/O 103 I/O 104 I/O 106
I/O GND 108 I/O 111 I/O 112 I/O 114 I/O 115
I/O 152
I/O I/O GOE I/O 116 VCC 1 127 GND 131 I/O 119 I/O 120 I/O 123 I/O 124
I/O I/O 140 VCC TOE 150 Y2 I/O 142 I/O 144 I/O 147
I/O GOE I/O 130 0 134 GND
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
1. NC pins are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package.
9
8
7
6
5
4
3
2
1
14
Specifications ispLSI 3256E
Part Number Description ispLSI
Device Family Device Number Speed 100 = 100 MHz fmax 70 = 70 MHz fmax
3256E - XXX X
XXXX
X
Grade Blank = Commercial Package Q = PQFP (With Heat Sink) QA = PQFP (Without Heat Sink) B320 = BGA Power L = Low
Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 100 100 ispLSI 100 70 70 70 tpd (ns) 10 10 10 15 15 15 ORDERING NUMBER ispLSI 3256E-100LQ1 ispLSI 3256E-100LQA ispLSI 3256E-100LB320 ispLSI 3256E-70LQ1 ispLSI 3256E-70LQA ispLSI 3256E-70LB320 PACKAGE 304-Pin PQFP (With Heat Sink) 304-Pin PQFP (Without Heat Sink) 320-Ball BGA 304-Pin PQFP (With Heat Sink) 304-Pin PQFP (Without Heat Sink) 320-Ball BGA
1. Converted to ispLSI 3256E-xxxLQA per PCN #03A-07.
Revision History
Date -- March 2007 Version -- 09 Previous Lattice releases. Updated Part Number Description and Ordering Information. Change Summary
15

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